INFORMATION TECHNOLOGY

The Athena Group, Inc.

Ancient Math System Delivers Breakthrough
in Digital Signal Processing

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Digital signal processing (DSP) technology is at the core of many electronic information and consumer systems and products. DSP interprets and relays information signals within electronic devices such as computers and cellular telephones. By the late 1990s, however, advances in semiconductors (electronic chips that run many electronic devices) were clearly outpacing DSP technology. In 1997, The Athena Group envisioned developing the next generation of DSP technology. Athena predicted that it could achieve a dramatic tenfold increase in information processing speed by developing smaller yet less expensive circuit processor or accelerator core designs. The company proposed to use a unique arithmetic schema called “residue number system” (RNS) to process information.

Athena was inspired to advance DSP technology by the company’s successful development and application of RNS to the Athena Signal Array Processor (ASAP), a project funded by the U.S. Air Force. However, due to the high-risk technical challenges and Athena’s status as a small company, private sector and internal funding were not available. In March 1997, Athena sought cost-shared funds from the Advanced Technology Program (ATP).

After receiving an ATP award, The Athena Group and its partner, VLSI Technology, worked from November 1997 to October 2000 to produce the next generation of DSP technology. At the conclusion of the project in 2000, The Athena Group had developed new RNS-enabled designs in semiconductor chips which featured low-cost production, reduced area, and reduced power consumption, which are important factors in extending the life of batteries and devices.

In 2000, Athena licensed this technology to Philips Semiconductor. Based on their ATP-supported technology advances, Athena developed new security technology called “TeraFire,” and, in February 2002, licensed it to Hifn, a leading network security company. By 2006, The Athena Group had significantly expanded its portfolio of licensees, which ranged from smaller customers such as Cryptek, to larger semiconductor manufactures like LSI Logic. These companies use the ATP-supported technology in many of their electronic products, enhancing products and services ranging from e-commerce to digital cameras to satellite communications. ATP assistance has helped Athena, a small company, to become a major player in DSP technology.

COMPOSITE PERFORMANCE SCORE
               (based on a four star rating)
* * *

Research and data for Status Report 97-01-0222 were collected during August – September 2006.

Athena Seeks to Advance DSP Technology The Athena Group, Inc. was a 9-employee company based in Gainesville, Florida, that, in 1997, envisioned major advances in digital signal processing (DSP).

DSP manages, analyzes, and interprets information and communication signals between electronic chips within a host of electronic devices such as computers, cellular telephones, and handheld products. The company believed that improving DSP technology was critical to

the electronic information and communications industries. Athena recognized that existing market demands for higher information bandwidth, increased functionality, smaller packages, and lower cost far exceeded the capability of existing DSP technology. DSP providers were forced to make trade-offs by either emphasizing speed at the expense of size and packaging issues, or stressing size and packaging issues with a significant loss in speed. These circumstances were obviously unacceptable for many emerging, high-end applications. Indeed, the need to develop superior DSP technology was critical to the semiconductor industry during the late 1990s since demand for media and communications related DSP functionality was a major growth driver for the industry. Athena Envisioned Using Algorithms to Develop Superior Processors The foundation of Athena’s vision to make DSP processors faster, smaller, and cheaper was based on newly developed algorithms derived from a fourth century form of arithmetic. This proven mathematical system is called the residue number system (RNS). RNS is a system, unlike mathematics used in conventional DSP, in which large calculations can be performed as a series of smaller calculations that can be executed independently and in parallel. Simply stated, Athena sought a superior yet less expensive method to execute DSP operations by breaking each computation into smaller, simpler computations. While much of the groundwork research on RNS was performed in the 1960s, it was not until the 1980s that this form of calculation experienced a revival of interest and potential application. Indeed, Athena began further developing and refining RNS technology in 1986. And although RNS had seen its greatest interest in academic circles, Athena was hopeful for its widespread commercial potential and consumer benefit, encouraged by the results from a previous RNS project. In 1995, the company had developed the Athena Signal Array Processor (ASAP) chip under U.S. Air Force Small Business Innovation Research (SBIR) funding. This processor demonstrated that even when using a custom or customer-specific design approach to satisfy the end-user’s specific needs and with an emphasis on speed, a speed-area increase of up to 50 times could still be achieved using RNS over conventional DSP arithmetic. Additionally, RNS demonstrated advantages in the areas of speed, high dynamic range (improving

the precision of computations), and compact silicon footprint (lower manufacturing cost and/or the ability to put more features on a chip). The RNS-enabled ASAP concept and chip demonstrated impressive advantages over conventional processing. However, despite these proven capabilities, the real challenge lay in refining and efficiently constructing high-speed, small-sized, RNS-enabled chips for multiple applications using commercially accepted design methodologies. Due to the complexities and numerous technical hurdles involved in this process, Athena was unable to secure private-sector funding for this project. While the original goal was to demonstrate the speed, size, and cost advantages of the residue number system (RNS), unexpectedly the improved function blocks proved superior and utilized less energy or power to operate. In March 1997 The Athena Group approached ATP with their concept for advancing DSP technology. Impressed by the company’s expertise in the area of DSP technology and their dedicated staff of engineers, ATP awarded cost-shared funding for this high-risk, high-reward research. Had ATP not provided support for this project, it is unlikely it would have been conducted. In November 1997, Athena and its partner, VLSI Technology, began work on the ATP project. VLSI was a leading application-specific integrated circuit vendor and would help to define the manufacturing technology and design methodology upon which the new math technology processors would be realized. The goal of the ATP project was to enhance RNS-enabled ASAP technology in order to achieve a tenfold increase in state-of-the-art DSP speed in one-third of the chip area at approximately one-half the cost. Athena believed that a major breakthrough in DSP speed, area, and cost was necessary to advance the next generation of communications, computer/multimedia, industrial, and defense systems, as well as the full range of electronic consumer products. Athena Seeks to Develop Residue Number System (RNS)-Driven Function Blocks At the heart of new circuit processor or accelerator core advancement was the development of superior, RNS-

driven DSP function blocks. Function blocks perform the basic automation functions within a computer or electronic device. Each function block processes input information according to a specific algorithm (such as image compression) and an internal set of controls. Function blocks then produce output information that is available for use within the same function block or is sent to other function blocks within the application. Essentially, function blocks are sets of connected “building blocks” that process both input and output information. Figure 1 illustrates this process. Figure 1. General schematic of a function block At the time of the ATP award, existing function blocks had to be constructed according to either speed or space/cost considerations. Function blocks that featured speed were often costly and took up large amounts of computer hardware space. But smaller, less costly function blocks did not process information as fast as the larger function blocks. Athena, supported by ATP, sought to bring the aspects of speed, cost, and space together in information processing function blocks. The project objectives for RNS-driven DSP function block development required that Athena engineers accomplish the following: · Maintain the speed-area advantage demonstrated in the original ASAP design. The information processing speed-area advantage demonstrated by the ASAP under the U.S. Air Force SBIR was 10 times that of conventional circuit chip processors. Athena needed to produce comparable results in its new function block designs. · Develop function blocks that are one-third the size and one-half the cost of existing function blocks. In order for this new technology to be considered a viable, usable product, significant improvements in size and cost had to be made. · Develop function blocks that are scalable and reusable. Blocks could be sized depending on

customer demands and could be used, regardless of the end design, in a variety of applications or platforms. Using RNS, Athena developed DSP function blocks that were capable of demonstrating a tenfold increase in processing speed over conventional DSP processors. In laboratory testing from November 1997 through October 1998, Athena proved that the performance of RNS-based multiplier accumulators (a processing unit that multiplies and accumulates the results of a multiplication) when compared to the equivalent conventional elements showed increases in speed that ranged from 2.3 times for the 32-bit RNS-driven multiplier accumulators to 28 times for the 64-bit RNS-driven multiplier accumulators. Based on this result, the project could move forward. Any results less than two times the speed would have ended the project. Athena Creates Smaller, Reusable, and Scalable Function Blocks In addition to achieving information processing speed requirements, Athena also developed signal processing function blocks that were both scalable and reusable. One improved function block was the Fast Fourier Transform (FFT), a type of function block used in many communication applications for digital signal processing to transform complex signals into simpler elements. In successfully applying RNS algorithms to FFT function blocks, Athena was able to reduce the power and chip area required to implement a particular level of FFT processing, thus allowing its customers to reduce manufacturing costs and increase the space dedicated to enhanced functionality on their chips. Athena was also able to successfully apply RNS to the Discrete Cosine Transform (DCT) function blocks, producing improved performance, chip area, and power consumption. The DCT is the function block that is at the heart of virtually all image and video compression, and is used in everything from digital television to digital cameras. While the DCT is common to both digital televisions and digital cameras, the performance, chip area, and power requirements for each of these applications are radically different: the camera must compress at most only one image per second but must run on batteries, while the television must decompress 60 images per second but does not have to run on batteries. Athena’s ability to balance performance, chip area, and power using its DSP technology allows it to

create solutions optimized for each of these scenarios. Importantly, by embedding the RNS technology in a function block that addresses an application’s specific requirements, Athena hides the extreme level of complexity of the RNS technology from the chip designer, which minimizes the cost of realizing the benefits of Athena’s RNS technology. The success that Athena achieved in realizing the speed, power, and chip area benefits of its DSP technology for specific, well-known functions such as DCT and FFT formed a foundation from which Athena has expanded its capabilities to implement other functions. By reusing design elements that were used to create these well-known, widely used functions, Athena was now able to design function blocks and chip architecture that could focus on unique application needs based on customer specifications. If, for example, the customer wanted a unique function for a cell phone or a computer to feature a particular size and cost, then that design would favor those elements over speed, and vice versa. Or a design might place equal emphasis on each of these elements. The RNS-driven function blocks provided an unprecedented high level of flexibility in achieving customer specifications. Athena Creates Low-Cost Accelerator Cores Athena was able to dramatically reduce both the area needed on the chip to power DSP, as well as the cost to design these circuits. While the original goal was to maintain ASAP processing speeds in commercial chip designs, using the newly available metrics of reusability and scalability, Athena was also able to address space and cost priorities. Regardless of how speed, space, and cost factors were prioritized, the company could design to customer specifications. When compared to existing accelerator cores, Athena’s flexibility was unparalleled. Athena was now able to design function blocks and chip architecture that could focus on unique application needs based on customer specifications. At the conclusion of the project in October 2000, Athena had achieved new and innovative circuit

processor/accelerator core designs that featured greater speed, less area, and lower cost, or a combination of these factors. None of Athena’s competitors could match the design capabilities of the company’s new ASAP DSP technology. Athena’s patent-pending RNS-enabled methodology was paving the way to superior DSP advancement. RNS Can Reduce Power Requirements In the process of developing these new function blocks, Athena discovered that the function blocks actually required less power to generate a greater number of computations when compared to existing function blocks. While the original goal was to demonstrate the speed, size, and cost advantages of RNS, unexpectedly the improved function blocks proved superior and utilized less energy or power to operate. In some applications, a tenfold reduction in power resulted when compared to conventional functional blocks. This dramatic power improvement was the result of the high degree of data and image compression produced by using RNS. Lower power produces less heat, which in turn allows for the removal of smaller cooling fans or even the complete elimination of cooling hardware. This development created even more device hardware space, allowing for denser circuitry placement and more compact circuit board designs. Reduction of power consumption also translated into cost savings both in power supplies and the cooling systems used to remove the waste heat. This power advantage would allow all mobile electronic devices that used accelerator cores or designs based on Athena’s RNS-operated function blocks to operate on less battery power, thereby extending the life and capacity of the batteries and the electronic device. In an era when computers and electronic devices are becoming increasingly more sophisticated and power intensive, the ability for a processor or processing system to operate on less power is a significant benefit. New Circuit Designs Enter the Market In 1999, partner VLSI was acquired by Philips Semiconductors, a change that could have presented an obstacle to the progress of the new technology. However, not only did Philips continue to support the project, they eventually became a customer for Athena’s ATP-funded technology. Indeed, after overcoming numerous high-risk

technical hurdles over a period of just 30 months, in mid-2000, Athena sold its first commercial license to Philips. Philips used the DSP information processing technology in three of its products: the Velocity RSP7/7+ platform used in digital camera operations, the Velocity RSP9 platform, and the Nexperia Advanced Prototyping Architecture platform. In 2002, Athena began extending the use of RNS technology into the developing area of information security. By 2006, both DSP information processing and TeraFire security processors/accelerators were being used by the technology industry in a variety of applications, such as e-commerce, digital cameras, wireless communications, video compression and public-key security. The explosive growth of the Internet gave rise to a new area of technology devoted to protecting information. By the late 1990s and early 2000s, servers needed to be able to process tens of thousands of new security requests per second. Unfortunately, state-of-the-art security processing systems could handle only a few hundred requests or sessions per second. Many of these systems required laborious security and user identification authorization steps. Additionally, existing information security processes required an immense amount of computation, which led to problems with the basic implementation for these security systems. Based on its new RNS-driven technology, Athena developed a line of cryptographic accelerators, which they called “TeraFire.”^1 The TeraFire accelerator line enables secure session communications across the Internet and via wireless devices. In February 2002, U.S.-based Hifn, a leading network security company, signed as a licensee for Athena’s TeraFire accelerator cores for placement in its products. While Athena originally envisioned advancing the next generation of DSP, its new designs achieved unexpected success with companies in the information security field as well as anticipated gains in the general application of DSP.

By 2006, both DSP information processing and TeraFire security processors/accelerators were being used by the technology industry in a variety of applications, such as e-commerce, digital cameras, wireless communications, video compression and public-key security. ASAP-based accelerators have been designed into satellite communications transmitters and receivers, secure fax machines, and general purpose security accelerators. Other markets under consideration are hearing aid manufacturers and general-purpose DSP manufacturers who find it attractive to embed high-performance accelerators in devices to boost performance in specific applications. In 2006, TeraFire had reached its third generation of development and was being used by some well-regarded technology companies, including Hifn, LSI Logic, and Cryptek. The speed and flexibility of Athena’s RNS-driven function block designs have resulted in computer chips that are reusable, scalable, and more compact. They have proven to be effective and useful to many U.S. companies in a wide variety of applications. Conclusion In 1997, The Athena Group foresaw major advances in digital signal processing (DSP) using an innovative information calculation system called residue number system (RNS). Athena envisioned a dramatic tenfold increase in information and data processing speeds over conventional mathematical functions. Such improvement was critical to the U.S. semiconductor chip industry because increased demands for functionality on semiconductor chips were outpacing the ability of DSP systems to process information. But because RNS processing technology was unproven on a mass commercial scale, Athena, a small company, was unable to attract or generate from within the necessary funding to support this research. In March 1997, Athena won an ATP cost-shared award. In November 1997, the company and its partner VLSI Technology began work on this high-risk, high-reward research. At the conclusion of the project in October 2000, Athena had successfully developed semiconductor chip function blocks using RNS algorithms. These newly designed function blocks were scalable and reusable

¹TeraFire is a registered trademark of The Athena Group.

and operated on significantly less space than function blocks using conventional mathematical processing. In addition to achieving the original project goals, Athena discovered an unexpected but highly significant benefit: their newly designed function blocks operated on significantly less power than conventional function blocks. In some designs, the reduction in power was as high as tenfold. Processing systems that require less power also extend the lives of the battery and the electronic device. Overall, Athena achieved technical success beyond its expectations, which led to the commercial application of its RNS-driven technology. In 2000, Athena licensed the technology to Philips Semiconductors, and, in February 2002, entered the information security domain by signing a licensing agreement with Hifn, a leading network security company. Athena’s information security products are marketed as “TeraFire.”

By 2006, Athena licensed its DSP information processing and TeraFire security information product designs to numerous customers, including Philips, Hifn, LSI Logic, and Cryptek. These companies use the ATP-supported signal accelerator cores in applications ranging from e-commerce to digital cameras. The Athena Group exceeded expectations in DSP technology development and subsequently identified valuable commercial applications for the technology.

PROJECT HIGHLIGHTS
The Athena Group, Inc.

Project Title: Ancient Math System Delivers Breakthrough in Digital Signal Processing (High Performance Applied-Specific Integrated Circuit Technology for Digital Signal Processing) Project: To develop the technology for a new class of digital signal processing (DSP) chips to enable up to a tenfold increase in speed over conventional DSP technology, in a smaller package, at a lower cost, with important applications in mobile communications and multimedia markets. Duration: 11/1/1997 - 10/31/2000 ATP Number: 97-01-0222 Funding (in thousands): ATP Final Cost              $1,859    81.7% Participant Final Cost      415    18.3% Total                            $2,274 Accomplishments: Over the course of the project, The Athena Group accomplished the following: · Developed DSP function blocks that were capable of demonstrating tenfold increases in processing speed over conventional DSP processors · Used the advanced efficiency of the residue number system (RNS) to reduce by two-thirds the area needed to implement information processing functions · Developed DSP information processing accelerators based on RNS-enabled arithmetic that could reduce the cost of a DSP processing unit by as much as 50 percent · Developed function blocks that were both scalable and reusable · Developed function blocks that used less power, by as much as tenfold, than conventional function blocks · Developed TeraFire security products based on RNS-enabled arithmetic

Commercialization Status: In 2006, both of Athena’s RNS-based designs, DSP information processing and TeraFire security processors/accelerators had been accepted by the technology industry. Both products are used in a variety of applications, such as e-commerce, digital cameras, wireless communications, video compression, and public-key security. In 2006, TeraFire had reached its third generation of development. TeraFire is used by some well-regarded technology companies, including Hifn, LSI Logic, and Cryptek. Outlook: The outlook for Athena’s technology is strong. The demand for information processing and security devices is high and is projected to continue to rise. Composite Performance Score: * * * Number of Employees: 9 at project start, 14 as of September 2006. Company: The Athena Group, Inc. 408 W. University Avenue, Suite 306 Gainesville, FL 32601 Contact: Monica Murphy Phone: (352) 371-2567 Publication: · Vogel, Mike. “Designing Chips.” Florida Trend, p. 12, April 2001.

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Research and data for Status Report 97-01-0222 were collected during August – September 2006.